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Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
Features
* 10 differential 3.3V LVPECL outputs * Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs * CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * CLK1 accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency: 350MHz * VCO range: 250MHz to 700MHz * External feedback for "zero delay" clock regeneration with configurable frequencies * Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) CLK1, 80ps (maximum) * Output skew: 150ps (maximum) * Static phase offset: -150ps to 150ps * Lead-Free package fully RoHS compliant * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8732-01 is a low voltage, low skew, 3.3V LVPECL Clock Generator and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8732-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8732-01 has a fully integrated PLL along with frequency configurable outputs. An external feedback input and outputs regenerate clocks with "zero delay".
ICS
The ICS8732-01 has multiple divide select pins for each bank of outputs along with 3 independent feedback divide select pins allowing the ICS8732-01 to function both as a frequency multiplier and divider. The PLL_SEL input can be used to bypass the PLL for test and system debug purposes. In bypass mode, the input clock is routed around the PLL and into the internal output dividers.
BLOCK DIAGRAM
CLK_SEL CLK0 nCLK0 CLK1 FB_IN nFB_IN
PIN ASSIGNMENT
FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN nQFB0 nQFB1 FB_IN QFB0 QFB1 VCCO VCC VEE VEE
0 1
0
/2 /4 /6 /8 /2 /4 /8 /12 /4 /6 /8 /10 /8 /12 /16 /20
QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QB0 nQB0 QB1 nQB1 QB2 nQB2 QB3 nQB3 QFB0 nQFB0 QFB1 nQFB1 VCCO QA0 nQA0 QA1 nQA1 VEE PLL_SEL VCCO QA2 nQA2 QA3 nQA3 VEE 1 2 3 4 5 6 7 8 9
PLL
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VCCO nQB3 QB3 nQB2 QB2 VEE MR VCCO nQB1 QB1 nQB0 QB0 VEE
PLL_SEL
DIV_SELA0 DIV_SELA1 DIV_SELB0 DIV_SELB1 FBDIV_SEL0 FBDIV_SEL1 FBDIV_SEL2
ICS8732-01
33 32 31 30 29 28
10 11 12
27 13 14 15 16 17 18 19 20 21 22 23 24 25 26
DIV_SELA1 DIV_SELA0 VCC VEE CLK1 nCLK0 CLK0 CLK_SEL VCCA nc DIV_SELB1 DIV_SELB0 VCC
MR
52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View
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REV. C MAY 31, 2005
Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
Type Description Output supply pins. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 8, 32, 39, 40 2, 3, 4, 5 6, 13, 17, 27, 34, 45, 52 7 9, 10, 11, 12 14 15 16, 26, 46 18 19 20 21 22 23 24 25 28, 29, 30, 31 33 35, 36, 37, 38 41, 42, 43, 44 47 48 49 50 51 Name VCCO QA0, nQA0, QA1, nQA1 VEE
Power Output
Power
Negative supply pins. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Core supply pins. Pulldown LVCMOS / LVTTL reference clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. Pulldown When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Analog supply pin. No connect. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs Pulldown nQx to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels. Differential feedback output pairs. LVPECL interface levels. Feedback input to phase detector for regenerating clocks with "zero delay". Feedback input to phase detector for regenerating clocks Pullup with "zero delay". Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Pulldown
PLL_SEL QA2, nQA2, QA3, nQA3 DIV_SELA1 DIV_SELA0 VCC CLK1 nCLK0 CLK0 CLK_SEL VCCA nc DIV_SELB1 DIV_SELB0 QB0, nQB0, QB1, nQB1 MR QB2, nQB2, QB3, nQB3 QFB1, nQFB1, QFB0, nQFB0 FB_IN nFB_IN FBDIV_SEL0 FBDIV_SEL1 FBDIV_SEL2
Input Output Input Input Power Input Input Input Input Power Unused Input Input Output
Pullup
Input
Output Output Input Input Input Input Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 0 0 0 0 0 PLL_SEL X 1 1 1 1 0 0 0 0 DIV_SELA1 X 0 0 1 1 0 0 1 1
FOR
QA0:QA3 OUTPUTS
Outputs QA0:QA3, nQA0:nQA3 Low fVCO/2 fVCO/4 fVCO/6 fVCO/8 fREF_CLK/2 fREF_CLK/4 fREF_CLK/6 fREF_CLK/8
DIV_SELA0 X 0 1 0 1 0 1 0 1
TABLE 3B. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 0 0 0 0 0 PLL_SEL X 1 1 1 1 0 0 0 0 DIV_SELB1 X 0 0 1 1 0 0 1 1
FOR
QB0:QB3 OUTPUTS
Outputs QB0:QB3, nQB0:nQB3 Low fVCO/2 fVCO/4 fVCO/8 fVCO/12 fREF_CLK/2 fREF_CLK/4 fREF_CLK/8 fREF_CLK/12
DIV_SELB0 X 0 1 0 1 0 1 0 1
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LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
FOR
TABLE 3C. CONTROL INPUT FUNCTION TABLE
Inputs MR 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_SEL X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FBDIV_SEL2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
QFB0, QFB1
Outputs QFB0, QFB1 nQFB0, nQFB1 Low fVCO/4 fVCO/6 fVCO/8 fVCO/10 fVCO/8 fVCO/12 fVCO/16 fVCO/20 fREF_CLK/4 fREF_CLK/6 fREF_CLK/8 fREF_CLK/10 fREF_CLK/8 fREF_CLK/12 fREF_CLK/16 fREF_CLK/20
FBDIV_SEL1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FBDIV_SEL0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TABLE 4A. QX OUTPUT FREQUENCY
W/FB_IN
= QFB0
OR
QFB1
fVCO CLK1 (MHz) Minimum 62.5 41.67 31.25 25 31.25 20.83 15.62 Maximum 175 (NOTE 2) 116.67 87.5 70 87.5 58.33 43.75 35
Inputs FB_IN QFB QFB QFB QFB QFB QFB QFB FBDIV_SEL2 0 0 0 0 1 1 1 FBDIV_SEL1 0 0 1 1 0 0 1 FBDIV_SEL0 0 1 0 1 0 1 0 Output Divider Mode /4 /6 /8 /10 /8 /12 /16
(NOTE 1) fREF_CLK x 4 fREF_CLK x 6 fREF_CLK x 8 fREF_CLK x 10 fREF_CLK x 8 fREF_CLK x 12 fREF_CLK x 16 fREF_CLK x 20
QFB 1 1 1 12.5 /20 NOTE 1: VCO frequency range is 250MHz to 700MHz. NOTE 2: The maximum input frequency that the phase detector can accept is 175MHz.
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LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 42.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VCC VCCA VCCO ICC ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3. 3 Maximum 3.465 3.465 3.465 165 15 Units V V V mA mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VIH Input High Voltage CLK1 CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR CLK1 CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx PLL_SEL CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx PLL_SEL Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VCC+ 0.3 VCC+ 0.3 1.3 0.8 Units V V V V
VIL
Input Low Voltage
IIH
Input High Current
VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150
150 5
A A A A
IIL
Input Low Current
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ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
Test Conditions CLK0, FB_IN nCLK0, nFB_IN CLK0, FB_IN nCLK0, nFB_IN VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for FB_IN, nFB_IN is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 1.0 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fREF Parameter Input Reference Frequency Test Conditions Minimum Typical Maximum 200 Units MHz
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Static Phase Offset; NOTE 1 Output Skew; NOTE 2, 3, 4 CLK0, Cycle-to-Cycle Jitter ; nCLK NOTE 3 CLK1 Test Conditions PLL_SEL = 3.3V, fREF = 100MHz, fVCO = 400MHz Minimum Typical Maximum 350 150 150 50 80 10 700 52 signal Units MHz ps ps ps ps ms ps %
t(O) tsk(o) tjit(cc)
-150
PLL Lock Time tL tR / tF Output Rise/Fall Time 20% to 80% 200 odc Output Duty Cycle fOUT 175MHz 48 All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: All outputs in divide by 4 configuration.
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LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V Vcc nCLK0, nFB_IN
V
VCC , VCCA , VCCO
Qx
SCOPE
LVPECL
nQx
CLK0, FB_IN
PP
Cross Points
V
CMR
VEE VEE -1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0:nQA3, nQB0:nQB3, nQFB0, nQFB1 QA0:QA3, QB0:QB3, QFB0, QFB1
nQx Qx nQy Qy
tsk(o)
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nCLK0 CLK0, CLK1 nFB_IN FB_IN
t(O)
VOH VOL VOH VOL
80% Clock Outputs
20% tR tF
STATIC PHASE OFFSET
nQA:nQA3, nQFB0, nQFB1 QA:QA3, QFB0, QFB1
OUTPUT RISE/FALL TIME
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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tcycle n+1
80% VSW I N G 20%
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LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
LVPECL OUTPUTS
drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to
3.3V
Zo = 50
125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
8732AY-01
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8732-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 3. POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
8732AY-01
BY
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
9
BY
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ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
pacitors should be physically located near the power pin. For ICS8732-01, the unused outputs can be left floating.
Zo = 50 + VCC R14 1K Zo = 50 -
LAYOUT GUIDELINE
Figure 5 shows a schematic example of the ICS8732-01. In this example, the CLK0/nCLK0 input is selected. The decoupling ca-
VCC VCCA R7 10 C16 10uF VCC Zo = 50 C11 0.1uF DIV_SELA1 DIV_SELA0 14 15 16 17 18 19 20 21 22 23 24 25 26 13 12 11 10 9 8 7 6 5 4 3 2 1
VCC R4 50 U1 ICS8732-01 R6 50 52 51 50 49 48 47 46 45 44 43 42 41 40 FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 R5 50
Zo = 50 LVPECL R1 50 R2 50 R3 50 DIV_SELB1 DIV_SELB0
DIV_SELA1 DIV_SELA0 VCC VEE CLK1 nCLK0 CLK0 CLK_SEL VCCA nc DIV_SELB1 DIV_SELB0 VCC
VEE nQA3 QA3 nQA2 QA2 VCCO PLL_SEL VEE nQA1 QA1 nQA0 QA0 VCCO
VEE FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN FB_IN VCC VEE nQFB0 QFB0 nQFB1 QFB1 VCCO
R10 50
R11 50
R13 1K
VEE QB0 nQB0 QB1 nQB1 VCCO MR VEE QB2 nQB2 QB3 nQB3 VCCO
27 28 29 30 31 32 33 34 35 36 37 38 39
R12 50
Zo = 50
Logic Input Pin Examples
VCC
+
Set Logic Input to '1'
RU1 1K
VCC
Set Logic Input to '0'
RU2 SP
Zo = 50
VCC=3.3V SP = Spare (i.e. not intstalled)
(U1-1)
VCC R8 50 R7 50
-
To Logic Input pins
RD1 SP RD2 1K
To Logic Input pins
(U1-8)
(U1-16)
(U1-26)
(U1-32)
(U1-39)
(U1-40)
(U1-46)
R9 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
Bypass capacitors located near the power pins
FIGURE 5. ICS8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE
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ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8732-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8732-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 165mA = 572mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.465V, with all outputs switching) = 572mW + 302mW = 874mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.874W * 36.4C/W = 102C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 8. Thermal Resistance JA for 52-pin LQFP, Forced Convection
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0C/W 42.3C/W
200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = VOH_MAX = VCCO_MAX - 1.0V (V
CCO_MAX
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 9.
JAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
47.1C/W 36.4C/W
500
42.0C/W 34.0C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
58.0C/W 42.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8732-01 is: 4916
8732AY-01
www.icst.com/products/hiperclocks.html
13
REV. C MAY 31, 2005
Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
52 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 E E1 e L ccc 0.45 0 --0.05 1.35 0.22 0.09 BCC MINIMUM NOMINAL 52 --1.40 0.32 -12.00 BASIC 10.00 BASIC 12.00 BASIC 10.00 BASIC 0.65 BASIC ---0.75 7 0.08 1.60 0.15 1.45 0.38 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8732AY-01
www.icst.com/products/hiperclocks.html
14
REV. C MAY 31, 2005
Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS8732AY-01 ICS8732AY-01T ICS8732AY-01LF ICS8732AY-01LFT Marking ICS8732AY-01 ICS8732AY-01 ICS8732AY-01 ICS8732AY-01LF Package 52 Lead LQFP 52 Lead LQFP 52 Lead "Lead Free" LQFP 52 Lead "Lead Free" LQFP Shipping Packaging tray 500 tape & reel tray 500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8732AY-01
www.icst.com/products/hiperclocks.html
15
REV. C MAY 31, 2005
Integrated Circuit Systems, Inc.
ICS8732-01
LOW VOLTAGE, LOW SKEW 3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET Description of Change Features Section - changed VCO min. from 200MHz to 250MHz. Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF. Qx Output Frequency Table - changed the CLK1 min. column to correlate with the VCO change. Absolute Maximum Ratings - changed VO to IO and included Continuous Current and Surge Current Added Differential Clock Input Interface in the Application Information section. Power Supply DC Characteristics Table - changed IEE from 240mA max. to 165mA max., and ICCA from 14mA max. to 15mA max. Power Considerations - recalculated Power Dissipation and Junction Temperatures to correspond with Table 5A. Updated LVPECL Output Termination diagrams. Added Schematic Layout. Block Diagram - changed REF_SEL to CLK_SEL. Ordering Information Table - corrected Tape & Reel Count to read 500 from 1000. Qx Output Frequency Table - changed NOTE 2 from "200MHz" to "175MHz". Features Section - added Lead Free bullet. Ordering Information Table - added Lead Free par t number and note. Power Supply DC Characteristics Table - corrected IEE to read ICC. 5/20/03 Date
Rev
Table T2 T4A
Page 1 3 4 5 8
B
C
T5A
5 8 10 1 15 4 1 15 5
6/23/03
C C C C C C T11 T4A T11 T5A
9/24/03 3/3/04 4/29/04 10/19/04 5/23/05 5/31/05
8732AY-01
www.icst.com/products/hiperclocks.html
16
REV. C MAY 31, 2005

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